1. Field of the Invention
The present invention relates to a method of testing an A-D converter having a comparator.
2. Description of the Background Art
FIG. 37 is a block diagram for illustrating a conventional technique of making a functional test of an A-D converter cell which is stored in an analog-digital combinational LSI, and FIG. 38 is a flow chart showing the method of the functional test.
Referring to FIG. 37, the analog-digital combinational LSI 12 stores an A-D converter cell 10 and a logic circuit 11. An analog circuit of the A-D converter cell 10 is supplied with a potential AVdd from a first power source 13 through an analog source terminal 1. On the other hand, a digital circuit of the A-D converter cell 10 and the logic circuit 11 are supplied with a potential DVdd from a second power source 14 through a digital source terminal 2.
In a ladder resistance in the A-D converter cell 10, points to be supplied with the highest and lowest potentials are supplied with potentials VRT and VRB from third and fourth power sources 15 and 16 through upper and lower reference source terminals 3 and 4 respectively.
The A-D converter cell 10 is supplied with an analog input voltage Vin from an analog source 17 through an analog voltage input terminal 5. Digital outputs obtained from the A-D converter cell 10 are supplied to the logic circuit 11, as well as to a data analyzer 19 through external test terminals 7 for executing a functional test. A computer 20 reads the digital output signals which are incorporated in a memory of the data analyzer 19, and performs arithmetic processing through an N-bit binary code signal line 21. For convenience of illustration, it is assumed here that the A-D converter cell 10 outputs 10-bit signals, and hence N=10. Therefore, the external test terminals 7 includes 10 terminals 7a, 7b, 7c, 7d, 7e, 7f, 7g, 7h, 7i and 7j.
The logic circuit 11 performs prescribed processing on the digital outputs obtained from the A-D converter cell 10 and supplies the same to a digital input/output terminal 9.
Further, the A-D converter cell 10 is connected to the ground 8, and supplied with a sampling clock for the A-D converter cell 10 and a clock to be supplied to the logic circuit 11 from a clock source 18 through a clock terminal 6.
As shown in FIG. 38, the first to fourth power sources 13 to 16 are turned on so that the potentials AVdd, DVdd, VRT and VRB are applied to the analog source terminal 1, the digital source terminal 2, the upper reference source terminal 3 and the lower reference source terminal 4 respectively at a step SP1.
At a step SP2, the sampling clock etc. from the clock source 18 are applied to the clock input terminal 6. On the other hand, the resolution of the analog input voltage Vin outputted from the analog source 17 is set at another step SP3.
At a step SP4, the analog input voltage Vin is stepwise supplied to the analog input voltage terminal 5 while being gradually increased by the resolution set at the step SP3.
At a step SP5, the digital outputs (binary data) of the A-D converter cell 10 obtained from the external test terminals 7 are stored in the memory of the data analyzer 19.
At a step SP6, the binary data are converted to decimal numbers from the memory of the data analyzer 19 by the computer 20. Nondefectiveness/defectiveness is determined at a step SP7 from the converted results.
FIG. 39 illustrates correspondence between binary codes and decimalized codes converted therefrom. It is assumed here that bits supplied to the external test terminals 7a and 7j are the least and most significant bits LSB and MSB respectively. The values of the decimalized codes are obtained by 7a.times.2.sup.0 +7b.times.2.sup.1 +7c.times.2.sup.2 +7d.times.2.sup.3 +7e.times.2.sup.4 +7f.times.2.sup.5 +7g.times.2.sup.6 +7h.times.2.sup.7 +7i.times.2.sup.8 +7j.times.2.sup.9.
FIG. 40 is a graph showing the relation between the analog input voltage Vin and the decimalized codes in case of a correct A-D converter cell 10. The width of the analog input voltage Vin corresponding to the decimalized codes is constant regardless of the values of the decimalized codes (excluding the decimalized codes of "0" and "1023"), and the decimalized codes are stepwise increased as the analog input voltage Vin is increased. In this case, a determination on nondefectiveness is made at the step SP7.
FIGS. 41 to 43 are graphs showing the relations between analog input voltages Vin and decimalized codes in a case illustrating missing codes. In each of these figures, a decimalized code "5" is missing and not all codes of "0" to "1023" are present. In such case, a determination on defectiveness is made at the step SP7.
As described above, the prior art is adapted to determine whether or not all prescribed values of decimalized codes are present, and hence it is necessary to obtain binary codes from the external test terminal 7. Due to the necessity of providing the external test terminal 7, the chip area of the semiconductor device is increased to increase the package size. Thus, the cost for the semiconductor device is disadvantageously increased.